1. Field of the Invention
The present invention relates to a method of manufacturing capacitors in semiconductor memory devices, and more particularly to a method for making a tantalum layer that is oxidized to form a fine tantalum oxide layer providing a large capacitance in a semiconductor capacitor having a limited volume.
2. Description of the Prior Art
In conventional methods, a thin Ta.sub.2 O.sub.5 layer, which was developed as a dielectric layer for storage electrodes in memory cells of highly integrated semiconductor devices such as 64M DRAMs, is formed by a chemical vapor deposition (CVD) method. Such a chemical vapor deposition method may include a low pressure chemical vapor deposition (LPCVD) method or a plasma enhanced chemical vapor deposition (PECVD) method.
In a typical LPCVD method, Ta(OC.sub.2 H.sub.5).sub.5 and O.sub.2 are used as reactive gases. After O.sub.2 is introduced into a reactive furnace to stabilize the pressure of the furnace, Ta(OC.sub.2 H.sub.5).sub.5 is introduced with Ar as a carrier gas, resulting in a deposited Ta.sub.2 O.sub.5 layer on the surface of a wafer in the furnace.
Ta(OC.sub.2 H.sub.5).sub.5 is thermally decomposed at a temperature of 170.degree. C., while the pressure and temperature of the furnace are maintained at 0.5 Torr and between 300.degree. and 470.degree. C., respectively.
A typical PECVD method employs an inorganic Ta based on TaCl.sub.5 and N.sub.2 O as reactive gases. TaCl.sub.5, which is a solid source, is evaporated at 120.degree. C. and then introduced into a reactive furnace. Once TaCl.sub.5 and N.sub.2 O gases are simultaneously introduced into the furnace to stabilize the pressure of the furnace, an arc is supplied to cause the reaction of the gases to deposit Ta on a wafer surface, wherein the etching rate becomes minimized and the leakage current becomes extremely decreased, with an R.F. power of 0.5 W/cm.sup.2. Consequently, such a PECVD method provides high density as well as relatively low carbon density, as compared with the LPCVD method. Furthermore, the pressure in the reactive furnace is maintained at about 0.8 Torr and the temperature is maintained at about 450.degree. C.
FIG. 1 is a series of partial sectional views illustrating a conventional method of fabricating a capacitor in a semiconductor memory device by the LPCVD and PECVD processes. As illustrated in FIG. 1(A), doped node electrode 2 (capacitor storage electrode) is formed on semiconductor substrate 1. As illustrated in FIG. 1(B), tantalum oxide layer 3 is deposited on node electrode 2 by a LPCVD or a PECVD method. As illustrated in FIG. 1(C), doped polysilicon 4 as a plate electrode of a capacitor is formed on tantalum oxide layer 3, forming a capacitor in a semiconductor memory device. Additionally, in the case of LPCVD processing, an annealing process may be effective to minimize the ratio of carbon contained in the layer.
FIG. 2(A) is a partial sectional view of a capacitor with a tantalum oxide layer formed by a conventional LPCVD method. FIG. 2(B) is a partial sectional view of a capacitor with a tantalum oxide layer formed by a conventional PECVD method.
As illustrated in FIG. 2(A), a conventional method of fabricating a capacitor by a LPCVD method includes the following steps: doped polysilicon electrode node 2 (capacitor storage electrode node) is formed on semiconductor substrate 1 and on insulator 5, which had been formed in an earlier step; tantalum oxide layer 3 is then deposited on capacitor storage electrode node 2 by an LPCVD method; and doped polysilicon 4 for a plate electrode is deposited on tantalum oxide layer 3.
As illustrated in FIG. 2(B), a conventional method of fabricating a capacitor by a PECVD method includes the following steps: doped polysilicon electrode 2 is formed on semiconductor substrate 1 and on insulator 5, which had been formed in an earlier step; tantalum oxide layer 3 is then deposited on capacitor storage electrode node 2 by a PECVD method; and doped polysilicon 4 for a plate electrode is formed on tantalum oxide layer 3. When tantalum oxide layer 3 is deposited by a PECVD method, silicon oxide layer 9 is formed under tantalum oxide layer 3. Such a silicon oxide layer also may be formed with an LPCVD method during an annealing step.
FIG. 3 is a schematic sectional view of a memory cell structure in a semiconductor device according to the conventional method, wherein the reference numbers denote: 1--a semiconductor substrate; 2--a capacitor electrode node; 3--a tantalum oxide layer; 4--a capacitor plate electrode; 5--a gate insulator; and 7--a gate electrode.
When tantalum oxide layer 3 is formed by CVD processes such as illustrated in FIG. 2(A), a silicon oxide layer (not shown) is formed under tantalum oxide layer 3 during this procedure. As the memory cell is completed as illustrated in FIG. 3, silicon oxide layer 9 is absorbed in tantalum oxide layer 3.
Since an organic tantalum compound is employed to form a thin tantalum oxide layer by an LPCVD process according to the conventional method of fabricating a capacitor in a semiconductor memory device, the ratio of carbon contained in the tantalum oxide layer may be increased, resulting in an undesirable increase of leakage current. Contamination also is likely to occur during the PECVD process for forming a thin tantalum oxide layer. In addition, a silicon oxide layer is naturally formed between the tantalum oxide layer and the capacitor storage electrode node, resulting in an undesired increase of the overall thickness of the capacitor.